1. Technical Field
The present disclosure relates to a programmable logic array (PLA), and more particularly, to a high-performance static PLA.
2. Discussion of the Related Art
A programmable logic array (PLA) is generally used in an instruction decoder block of a processor or a control block of a finite state machine (FSM), which is typically complex, in order to increase an operation speed or reduce a chip area. The PLA generally includes an AND plane and an OR plane, which are connected to each other in series.
The PLA is classified into two types: a dynamic PLA and a static PLA. An example of the dynamic PLA is disclosed in U.S. Pat. No. 4,894,564, and an example of the static PLA is disclosed in U.S. Pat. No. 4,728,827. In general, while the dynamic PLA has a high operation speed, it has a high power consumption and a large amount of noise because the dynamic PLA is operated in synchronization with a clock signal having a short duration. In contrast, the static PLA has a low power consumption, but also has a low operation speed.